Computer systems typically include a central processing unit (CPU), high-speed devices (e.g., host cache memory and graphics controllers), and peripheral buses (e.g., peripheral component interconnect (PCI) or PCI Express (PCIe) bus) and on-chip integrated peripheral components (e.g., network interface controller, universal serial bus ports, flash memory, and audio devices). Some computer systems have a host interface that includes a memory controller hub and an input/output (I/O) controller hub. The memory controller hub connects the CPU to the high-speed components of the computer system via a coherent interconnect, which may be implemented by a front side bus or a serial interface, such as QPI (Intel® QuickPath Interconnect) or cHT (coherent HyperTransport). The I/O controller hub connects the memory controller hub to the peripheral buses and the integrated peripheral components via a hub interconnect. The peripheral components communicate with the I/O controller hub in accordance with a peripheral bus protocol. For example, in modern Intel® hub architectures, peripheral components typically communicate with the CPU via the PCI communication protocol or the PCIe communication protocol.
The host cache memory (also referred to as a “cache”) is a local, high-speed memory that increases system performance by fetching and storing data that is located adjacent to the requested piece of data from a lower-level cache or a main memory. The host cache memory typically includes status bits that indicate the status of each cache line in order to maintain data coherency throughout the computer system. For example, in accordance with the “MOESI” cache coherency protocol, the status bits indicate the state of the associated cache line (e.g., owned (O), modified (M), exclusive (E), shared (S), or invalid (I)).
In many computer systems, data is transferred from the CPU to peripheral components using an I/O operation that typically involves moving the data to the main memory, and then reading the data from the main memory by the CPU or the peripheral components. For example, in transferring output data from the CPU to an I/O device, the CPU typically creates the output data, transfers the output data to the main memory, and stores pointers (also referred to as descriptors) to the output data in a known location. The CPU then issues a “door bell” event that notifies the I/O device that the output data is ready to be transmitted. In response to the doorbell event, the I/O device uses the pointers to transfer the output data from the main memory to the I/O device. New processor and I/O hub architectures allow transfers to occur directly from caches in addition main memory.
What are needed are apparatus and methods that provide improved I/O communications with reduced CPU involvement.